Embark on a challenge to design critical electrical aspects of modern electronic systems using virtual prototyping techniques and numerical simulation CAE tools.
The 7th edition of TIEplus Signal & Power Integrity Challenge will take place on the 9th of May 2023 at Hotel Perla, Timisoara, Romania
Subject brief is published.
Asses the difficulty of the challenge and decide if you are up to the task.
3rd of April - 7th of April 2023
Full subject requirements are published. This marks the beginning of the 15 day period available to solve the challenge.
18th of April - 2nd of May 2023
Technical solution presentation.
Top contestants will be awarded with a certificate of competency.
9th of May 2023
Ensure signal integrity in a Video Processing Unit implemented using a NXP® System-on-Module connected to an external MIPI CSI-2® camera module.
Define the PCB stack-up and routing directives for the Main Board based on the MIPI D-PHY CSI-2 specification and perform a transient channel simulation evaluating the eye diagram at the receiver.
Provide S-parameter channel characterization, analyze differential and common-mode impedance profiles and evaluate compliance to frequency-domain requirements.
Design a single PCB in rigid-flex technology with Polymide based substrate for the functional modules of an augmented reality headset system.
Define the routing strategy and directives for the Sub-LVDS video interface, including differential via pattern design to match differential pair routing impedance, evaluate intra-pair skew requirements and signal quality.
Analyze the thermal distribution of the PGU board based on equivalent thermal network, evaluate noise budget, define DC IR drop and AC design targets and evaluate the PDN performance.
Design the LVDS channel to meet signal integrity requirements and the power delivery network for the 1V8 power rail to meet specifications of supply voltage in a simplified system architecture of a space cube satellite.
The PCB is divided into 5 functional modules (RF, Power, Processing, ADC and Image Sensor). Route the LVDS interface and power delivery network (including capacitors) for the 1V8 power rail and perform post-layout transient SI-PI co-simulation to validate and optimize the design.
Provide full channel PCIe routing recommendations for a FPGA graphic accelerator card connected to a server motherboard via a standard PCIe edge connector.
Verify channel compliance using S-parameter extraction and assess the impact of random jitter on differential signaling timing parameters.
Design and verify the power integrity solution for a 1.5V DDR3 supply rail in a SoC based graphical processing unit to meet ripple noise requirements under maximum transient load conditions.
Signal integrity analysis of a multi-board high resolution image acquisition system for quality compliance testing.
